The Opportunity 

In this role, you will be part of the Central Engineering team playing a key role in defining ESD requirements and verifying ESD solutions for Foundational IP, SerDes IP, and SOCs and continuing through to ESD qualification. You will work closely with the PD(Physical Design), Electrical Engineering, and SOC(System On Chip) teams to provide support from the initial design phase through failure analysis, issue root cause determination, and the development of corrective actions. 

 You will be responsible for the development of analog circuit IP to customer specifications including the generation and delivery of final EDA views for the IP.  Typical circuits to be developed include biasing blocks, over-voltage/over-current protection circuits, regulators, amplifiers, switches, and a range of closed loop feedback circuits.  

Responsibilities-  

• Perform ESD design reviews and provide the required technical guidance for analog, foundational IP, SOCs, and qualification test chips for multiple technology nodes ranging from 45nm to 3nm across major foundry platforms to maximize both performance and ESD protection robustness. 

• Validate and characterize ESD circuits using Calibre PERC, TLP-based SPICE simulation, and any other useful methods. 

• Design enablement of ESD protection schemes for analog design like SerDes. This will include understanding ESD protection design, latch-up, transient latch-up as well as ESD design verification and EDA tools. 

• Continue the development of “best practices” for ESD in the technologies being supported. 

• Development and support of EDA tools for ESD design checking. 

• Development of analog circuits like Driver/Receiver, Serializer/De-serializer, VCO, Charge Pump, Clock Divider, PFD, Bandgap, ADC/DAC, and Voltage Regulators. 

Education, Knowledge, Skills and Abilities: 

• Bachelor’s or Master’s degree and/or PhD in Electrical/Electronic Engineering, Microelectronics or related fields and 12-18 years of related professional experience. 

• Advanced knowledge of on-chip ESD protection circuit design 

• Advanced knowledge of CAD design tools such as Cadence and SPICE 

• Applicant should have sufficient design experience to be able to effectively review designs and communicate ESD design deficiencies to product design engineering. 

• Advanced knowledge of ESD relevant device physics such as snap-back and other high-level injection phenomenon/device operations 

• Fully familiar with industry ESD test standards and latest developments. 

• Comprehensive simulation skills in Cadence including PEX, Monte Carlo, and Corner analysis. 

• Derive design specifications from customer requirement. 

• Detailed knowledge in standard analog cell design including bandgaps, op-amps, detectors, regulators, precision current source and amplifiers. 

• ESD Design